Sr Principal Application Engineer

4 weeks ago


Toronto, Canada Cadence Full time

Sr Principal Application Engineer – Synthesis/STA/DFT At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This individual is the primary focal point for technical issues, questions, and discussions for a given project. Leads technical discussions with customers and is the primary technical interface with the Cadence PM. Capable of influencing outcomes among customers, R&D and Cadence technical team members. We need a pro‑active, enthusiastic, customer‑facing solution engineer who is an expert in circuits, design and timing analysis. This person will be focused on working with the customer in the Signoff solution space. Responsibilities Primary focal point for technical issues and questions for a given project. Leads technical discussions with customers and serves as technical interface with Cadence PM. Mentors other designers on technical topics for the project. Consults with clients and delivers results with minimal day‑to‑day guidance. Reviews, documents and resolves project technical issues; escalates to Project Management when appropriate. Understands Cadence semi‑custom IC tools; experience with competitive tools is beneficial. Guides and directs design reviews; has final authorization on design issues. Identifies technical skills that need development and recommends resources. Assesses technical impact of changes to evaluate feasibility and estimate effort required. Leads process improvement initiatives for technical projects and supports PM in developing business cases for improvement projects. Qualifications BS or MS in Electrical Engineering with 10+ years of industry experience in design and EDA (Digital Implementation/Signoff). Experience using digital software with at least one major EDA vendor flow; automation skills using Perl, Tcl, and shell scripting are essential. Strong analytical and problem‑solving skills covering digital implementation. Proven track record of working in a fast‑paced environment. Excellent customer interaction and presentation skills. Understands ASIC design implementation process and steps. Experience with synthesis tools (Genus, RTL Compiler, Design Compiler). Hands‑on experience with test products (Modus, Encounter Test, Logic Vision, DFT Compiler, etc.). Strong STA and SDC debugging abilities. Low‑power analysis and DFT clock design/analysis experience is a plus. Ability to understand and write RTL (System Verilog, Verilog, VHDL). Role Details Seniority level: Mid‑Senior level Employment type: Full‑time Job function: Education and Training Industry: Software Development We welcome applications from candidates with disabilities and in equity‑seeking groups. If you have accessibility needs during the application and interview process, please let us know. #J-18808-Ljbffr



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