Digital Logic Design Engineer

Overview 6 days ago Be among the first 25 applicants This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $124,000.00/yr - $186,000.00/yr What you do at AMD changes everything At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role We are searching for a senior RTL engineer to join the DDR PHY design team. This is an exciting opportunity to be a member of the Memory IO design team responsible for defining, specifying, and implementing RTL for the next generation of high-speed DDR and inter-chip IO IP for AMD’s graphics and semi-custom products. The Person The successful candidate will possess: Excellent analytical and problem-solving skills along with attention to detail Must be a self-starter, able to drive tasks independently and efficiently to completion Strong/effective communication skills Enthusiastic team-first mentality Key Responsibilities Analyze complex digital design problems and propose solutions. Microarchitectural design and RTL implementation of IP features. Drive/develop ASIC design flows and scripts Create microarchitecture specifications Work with the Design Verification team to ensure functional correctness Work with the Physical Design team to ensure proper implementation of the design Recommend improvements, optimization, and power saving enhancements Collaborate with Firmware team to develop firmware sequences and algorithms Support silicon bring-up and diagnostics Preferred Experience Proven experience in digital design from specification to successful silicon Experience in high-speed interfaces such as DDR, GDDR, HBM, and/or high-speed SERDES Experience in designs with multiple power domains Experience in designs with multiple clock domains Experience in industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, power estimation, etc. Progressive experience in RTL Design. Mixed signal RTL experience is a plus Exposure to leadership or mentorship is an asset Academic Credentials Bachelors or Master in Electrical Engineering or similar is preferred. Location Vancouver, Canada; Markham, Canada Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Seniority level Mid-Senior level Employment type Full-time Job function Industries: Semiconductor Manufacturing Referrals increase your chances of interviewing at AMD by 2x Get notified about new Logic Design Engineer jobs in Vancouver, British Columbia, Canada. Design Verification - Flow and Methodology Engineer Principal Engineer - CAD Physical Verification Burnaby, British Columbia, Canada 1 week ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. #J-18808-Ljbffr