Layout Design, Staff Engineer

2 months ago

Markham, Canada Synopsys, Inc. Full time

Job Description and Requirements

As a Staff A&MS Layout Engineer, you will collaborate in the development of advanced analog integrated circuit designs using the best-in-class Synopsys suite of tools. You will be working with local and global SERDES teams in developing layout for complex analog mixed-signal designs in the latest technology nodes. In your role, you will be responsible for taking on top-level block ownership and the creation of highly complex blocks. As a member of our Solutions IP Design Group, you will be developing IP in various technology nodes and foundries for various customers in a fast-paced environment.

Responsibilities and Duties

  • Leading and managing top-level blocks
  • Coordinating with other layout team members for top-level integration as well as designing and reviewing layout designs
  • Collaborating with the circuit team for feasibility layout of new products
  • Optimizing layout designs for performance, power, and area
  • Working with R&D experts to perform layout verification and resolve any design-related customer issues

Qualifications

  • BSEE or MSEE with at least 4 years of direct industry experience
  • In-depth knowledge of layout of analog and mixed signal CMOS circuits
  • Proficient with full custom analog layout design tool: Custom Compiler (or equivalent)
  • Prior knowledge and proficiency of schematic driven layout editor tools such as Custom Compiler SDL or Virtuoso XL
  • Must have a solid working knowledge of DRC, LVS and be able to debug results from ICV tools
  • Experience with advanced FinFET nodes is required
  • Ability to use foundry design rule manuals to debug DRC errors is required
  • Good written and verbal English skills
  • Experience with TCL, SKILL, PERL, Python or other language scripting is a plus
  • In-depth experience with regards to:
    • Layout design with consideration for reliability (EMIR/DFM)
    • Layout design to optimize for parasitic layout effects (matching/proximity effects)
    • Layout optimization for signal integrity (clock/data routes, differential routing, shielding)
    • Implementation of ESD design constraints, latch-up risk mitigation
    • Experience with PERC is a plus
  • Excellent communication skills and ability to interact with cross-functional teams
  • Experience with the following tools is a plus:
    • Jira/Atlassian
    • ICV Work Bench
    • ICC/ICC2/Fusion Compiler

This position is based in Canada. Candidates must have legal work status in Canada and be able to work in-office in a hybrid work model.

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