Lead ASIC/FPGA Designer: Verilog, CDC

Senior ASIC/FPGA Designer: Verilog, CDC & Synthesis Net2Source (N2S) Ottawa, ON, CA A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This role requires extensive experience (15+ years) in ASIC design and a bachelor’s degree in engineering or computer science. Key skills...

Senior ASIC/FPGA Designer: Verilog, CDC & Synthesis Net2Source (N2S) Ottawa, ON, CA A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This role requires extensive experience (15+ years) in ASIC design and a bachelor’s degree in engineering or computer science. Key skills...

Delivery Manager @ Infotree | Driving Client Success TOP MUST HAVE SKILLS: ASIC RTL Design Clock Domain Crossing (CDC) Analysis RTL Synthesis Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog...

Delivery Manager @ Infotree | Driving Client Success TOP MUST HAVE SKILLS: ASIC RTL Design Clock Domain Crossing (CDC) Analysis RTL Synthesis Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog...

Duration 12 months About the role Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science. Required Experience Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills...

Job Description:ASIC RTL Design.Verilog / SystemVerilog.Clock Domain Crossing (CDC) Analysis.Functional simulation debug.RTL Synthesis.Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer scienceExperience in front-end ASIC design EDA flows including: Client Design/Fusion Compiler, Client VCS...

A global staff augmentation firm is seeking a Digital ASIC/FPGA Designer with over 15 years of experience and a bachelor's degree in engineering or computer science. The role requires excellent RTL ASIC/FPGA design skills in Verilog and System Verilog, along with knowledge of networking standards and experiences with design tools. This position offers the...

A leading technology staffing firm is looking for a Digital ASIC/FPGA Designer in Ottawa, Canada. This hybrid role requires extensive experience, specifically in ASIC RTL design and proficiency in Verilog/SystemVerilog. The ideal candidate will have 15 years of experience, a Bachelor's degree in engineering or computer science, and skills in scripting...

A global workforce solutions leader in Ottawa is seeking a Mid-Senior level Digital ASIC/FPGA Designer for a 12-month contract. This role requires extensive experience (15+ years) in ASIC design and a bachelor's degree in engineering or computer science. Key skills include ASIC RTL design, Verilog, and RTL synthesis. The pay ranges from $90 to $100 per hour,...

A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This position requires at least 15 years of experience in ASIC design and a bachelor’s degree in engineering or computer science. Key skills sought include ASIC RTL design, Verilog, and RTL synthesis. The pay ranges from $90...