Senior ASIC/FPGA Designer: Verilog, CDC

Senior ASIC/FPGA Designer: Verilog, CDC & Synthesis Net2Source (N2S) Ottawa, ON, CA A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This role requires extensive experience (15+ years) in ASIC design and a bachelor’s degree in engineering or computer science. Key skills...

Delivery Manager @ Infotree | Driving Client Success TOP MUST HAVE SKILLS: ASIC RTL Design Clock Domain Crossing (CDC) Analysis RTL Synthesis Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog...

Delivery Manager @ Infotree | Driving Client Success TOP MUST HAVE SKILLS: ASIC RTL Design Clock Domain Crossing (CDC) Analysis RTL Synthesis Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog...

A global workforce solutions leader in Ottawa is seeking a Mid-Senior level Digital ASIC/FPGA Designer for a 12-month contract. This role requires extensive experience (15+ years) in ASIC design and a bachelor's degree in engineering or computer science. Key skills include ASIC RTL design, Verilog, and RTL synthesis. The pay ranges from $90 to $100 per hour,...

A global staff augmentation firm is seeking a Digital ASIC/FPGA Designer with over 15 years of experience and a bachelor's degree in engineering or computer science. The role requires excellent RTL ASIC/FPGA design skills in Verilog and System Verilog, along with knowledge of networking standards and experiences with design tools. This position offers the...

Duration 12 months About the role Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science. Required Experience Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills...

Job Description:ASIC RTL Design.Verilog / SystemVerilog.Clock Domain Crossing (CDC) Analysis.Functional simulation debug.RTL Synthesis.Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer scienceExperience in front-end ASIC design EDA flows including: Client Design/Fusion Compiler, Client VCS...

This range is provided by Net2Source (N2S). Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $90.00/hr - $100.00/hr Direct message the job poster from Net2Source (N2S) Join a Global Leader in Workforce Solutions – Net2Source Inc. Who We Are Net2Source Inc. isn't just another staffing...

A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This position requires at least 15 years of experience in ASIC design and a bachelor’s degree in engineering or computer science. Key skills sought include ASIC RTL design, Verilog, and RTL synthesis. The pay ranges from $90...

A global workforce solutions leader in Ottawa is seeking a Mid‑Senior level Digital ASIC / FPGA Designer for a 12‑month contract. This position requires at least 15 years of experience in ASIC design and a bachelor’s degree in engineering or computer science. Key skills sought include ASIC RTL design, Verilog, and RTL synthesis. The pay ranges from $90...