Design Verification Engineer
2 weeks ago
Job Title: Lead Design Verification Engineer (4 openings)
Duration: Fulltime
Location: Vancouver, British Columbia, Canada (Onsite only)
Experience: 8 to 15 years
Job Description:
Experience in SOC level verification.
Experience in PCie or Nvme.
Experience with SV-UVM methodology.
Experience on developing testbench and all TB components.
Experience on high-speed interface: PCIe, USB.
System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects.
by Jobble
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