Design Verification Engineer

2 weeks ago

Markham, Canada LanceSoft, Inc. Full time

Pay Rate: $100.00/hr to $125.00/hrLocation: Markham, ON CanadaThe Role:The team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced ASIC Design Verification engineer, who will be involved in different aspects of verification activities. The candidate will manage/utilize a variety of verification components to ensure the robustness of RTL designs.RESPONSIBILITIES:• Maintaining and enhancing verification environment and regression workflow• Triaging and debugging regression results• Analyzing test plan coverage• Writing, modifying, and maintaining test cases and libraries in SystemVerilog/UVM/RubyPERSONAL QUALITIES AND KEY SKILLSSuccessful candidate should possess the following personal qualities and technical skills (5+ years):• Experience with SystemVerilog, Verilog and C/C++ is a must• Strong understanding of the UVM-based verification methodology• Experience with Low Power Verification and debug methodology is a must• VCS/DVE familiarity is necessary.• Ability to juggle multiple on-going tasks at a time.• Strong, independent working ability• Strong teamwork and communication skills• Good attention to detail and creative thinking ability

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    Markham, Canada LanceSoft, Inc. Full time

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    Markham, Canada LanceSoft, Inc. Full time

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    2 weeks ago

    Markham, Canada LanceSoft, Inc. Full time

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    2 weeks ago

    Markham, Canada LanceSoft, Inc. Full time

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    1 month ago

    Markham, Ontario, York region, Canada LanceSoft, Inc. Full time

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    Markham, Ontario, York region, Canada LanceSoft, Inc. Full time

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    Markham, ON, Canada LanceSoft, Inc. Full time

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    3 days ago

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    Markham, ON, Canada LanceSoft, Inc. Full time €100 - €125

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    3 weeks ago

    Markham, Ontario, Canada LanceSoft, Inc. Full time

    **Role Summary**The team at LanceSoft, Inc. is seeking an experienced ASIC Design Verification Engineer to contribute to the success of our projects. The ideal candidate will have a strong understanding of SystemVerilog and Verilog, with experience in UVM-based verification methodology.Main Responsibilities:• Maintain and enhance verification environments...

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