Design Verification Engineer

3 days ago

Vancouver, Metro Vancouver Regional District, Canada TetriQ Solutions PVT LTD Full-time $90,000 - $120,000 Contract

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Summary

We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

  • Develop verification environments and testbenches using SystemVerilog and UVM.
  • Create and execute functional, regression, and constrained-random tests.
  • Analyze functional/code coverage and drive coverage closure.
  • Debug RTL and simulation failures and work with design teams to resolve issues.
  • Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
  • Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills

  • Strong SystemVerilog & UVM experience.
  • Solid understanding of RTL, digital design, and ASIC/SoC verification.
  • Experience with simulation tools such as VCS, Xcelium, or Questa.
  • Strong debugging and scripting skills.
  • Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.