Expert Design Verification Engineer Role
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Key Responsibilities
• Design verification environments with SystemVerilog and UVM
• Execute and analyze functional regression tests
• Debug RTL and collaborate with design teams
• Confirm protocol accuracy for AMBA/AXI, PCIe, Ethernet
• Automate test processes using Python or Shell scripting
Requirements:
• Strong proficiency in SystemVerilog and UVM
• Solid grasp of ASIC/SoC verification methodologies
• Experience using tools like Xcelium or Questa
• Demonstrated debugging and scripting capabilities
• Degree in Electrical, Electronics, or Computer Engineering Apply your verification expertise to advance digital design excellence in our team.
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