ASIC IP Digital Design Verification Engineer

6 days ago

Markham, Ontario, Canada AMD Full time
We are seeking an adaptive and self-motivated ASIC IP Digital Design Verification Engineer to drive and improve AMD's abilities to deliver high-quality, industry-leading technologies to market. Job Description

At AMD, we care deeply about transforming lives with our technology to enrich our industry, communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences.

We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

The Role

We are looking for a talented individual to join our growing team as an ASIC IP Digital Design Verification Engineer. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver high-quality, industry-leading technologies to market.

Key Responsibilities
  • Design Verification of digital design blocks
  • Study high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in-depth understanding of new features or changes proposed in new projects
  • Create test plans that outline required verification work for projects
  • Produce verification code that tests RTL design functionality using UVM as per test plan
  • Write cover points to ensure verification items are properly exercised
  • Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing
  • Learn and use Formal Verification techniques as needed
  • Manage and monitor regressions for team's blocks and fix errors in failing tests
  • Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases
  • Write and edit scripts to automate verification as needed
  • Regular review and sign-off of design verification work at key project milestones
  • Collaborate with other senior DV engineers in the team, Program Managers, and mentor juniors, interns, and new-hires
Preferred Requirements
  • Solid fundamental understanding of Computer Architecture and Digital Design concepts
  • Strong background in OOP coding techniques
  • Familiarity with scripting languages: perl, tcl, ruby, Bash, python, etc.
  • Preferred to have prior experience with Verilog or SystemVerilog and UVM
Academic Credentials
  • Undergrad degree required. Bachelors or Masters degree in Computer or Electrical Engineering, Computer Science, Engineering Science, or similar preferred

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