Memory System Verification Engineer

4 weeks ago

Vancouver, British Columbia, Canada AMD Full time
Design Verification Engineer at AMD: Transform lives with AMD technology, enriching our industry, communities, and world. We build great products accelerating next-generation computing experiences. We push innovation limits to solve world challenges, striving for execution excellence, being direct, humble, collaborative, and inclusive.

Design and develop the definition, design, and development phase of industry-leading Memory IP and overall memory subsystem. Verify memory subsystems across multiple product lines, including pre-silicon production level firmware verification.

As a passionate and experienced Verification engineer, join AMD's Memory IO team to tackle advanced engineering challenges. Collaborate across the AMD organization with strong interpersonal and communication skills.

Key responsibilities:

* Excellent knowledge of C, C++, SystemVerilog, UVM object-oriented design, and scripting languages.

* Experience in ground-up development and verification using UVM/SystemVerilog, with IP and Subsystem verification as the main objective using VCS.

* Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification.

* In-depth knowledge of code and functional coverage constructs, as well as test plan to coverage relationships.

* Development and debug of co-verification environment with production-level firmware.

* Development and maintenance of test suites through firmware feature set modification and custom transactor-based stimulus development.

* Ability to adapt and learn new toolsets and frameworks, making updates as needed.

Preferred experience:

* Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench.

* Knowledge and development of monitors and checkers, and/or experience developing SVA/OVL and synthesizable assertions.

* Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller verification.

* Understanding and experience utilizing architectural models.

* Knowledge of SystemC and Python.

* Zebu Emulation verification and debug experience.

* Memory VIP integration, initialization, and debug experience.

* End-to-end verification experience from front-end verification through lab bring-up.

* Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware-level clocking and multi-domain simulation synchronization.

* Strong knowledge of Git and Perforce.

* Development and maintenance of regressions as well as coverage databases.

Additional experienced desired:

* SoC IP knowledge and architectural understanding of the purpose of each IP.

* Bachelor's degree in Electrical or Computer Engineering and relevant experience, or a Master's or PhD degree in Electrical or Computer Engineering with relevant experience.

Location: Vancouver, BC, Canada

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