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Design Verification Engineer
4 weeks ago
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD is looking for a Verification Architecture and Methodology Engineer willing to take on the challenge of becoming part of the PCIe Sub-System team. In this role, you will work with Verification and Design experts to build PCIe subsystem topology for each program, setting up testing environments in various configurations, developing verification components, verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code, as well as support various teams including but not limited to SoC, DFX, FW, emulation and IP teams.
THE PERSON:
A successful candidate shall have a passion for modern, complex processor architecture, digital design, and verification in general. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBILITIES:
- Work with design and DV architects on building the best-fit topology based on SoC requirements.
- Work with design engineers on building the subsystem for SoC deliverables.
- Construct testbench in different configurations across IP teams and subsystem teams.
- Define verification methodology for IP teams and subsystem teams and guide the teams on reusability and portability in the UVM test environment.
- Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of Sub-System level IP interoperability.
- Build testbench components as well as develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
- Be a part of performance verification taskforce working on bandwidth, throughput and latency in PCIe Sub-System.
- Lead teams and mentor team members on DV implementation, deployment and debug for different tasks.
- Supervise team members on DV and PV for PCIe subsystem across multiple global sites.
- Support all sub-teams globally in PCIe subsystem organization and SoC teams.
PREFERRED EXPERIENCE:
- Strong background in ASIC Design Flow
- Expertise in Design Verification in any methodology.
- Proficient in SystemVerilog and scripting languages like Python, Perl, Ruby, Makefile, shell.
- Experience verifying complex designs using UVM, OVM or VMM
- Proficient in debugging firmware and RTL code using simulation tools
- Automating workflows in a distributed compute environment.
- Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB or Ethernet is a plus
- Experience with verification of Hardware-Firmware interaction is highly desirable
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong analytical and problem-solving skills with pronounced attention to detail
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: Markham, Vancouver, Ottawa
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
