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Design Verification Engineer

4 weeks ago

Markham, Ontario, Canada LanceSoft, Inc. Full time

Pay rate range:$75/hr to $100/hr on T4

Job description:

KEY RESPONSIBILITIES:


• Develop/Maintain tests for functional verification with UVM verification at the subsystem level


• Build testbench components to support the next generation IP


• Maintain or improve current test libraries to support IP level testing


• Technically lead IPs in Control Fabric,


• Have exposure to AXI protocol and Bootcode Verification


• Provide technical support to other teams

PREFERRED EXPERIENCE:


• Experience in C/C++


• Experience in SV and UVM


• Good scripting knowledge in Perl, Ruby and Makefile


• Familiarity with System Verilog and modern verification libraries like UVM

ACADEMIC CREDENTIALS:


• Bachelors or Masters degree in computer engineering/Electrical Engineering

About LanceSoft

LanceSoft is rated as one of the largest staffing firms in the US by SIA. Our mission is to establish global cross-culture human connections that further the careers of our employees and strengthen the businesses of our clients. We are driven to use the power of our global network to connect businesses with the right people, and people with the right businesses without bias. We provide Global Workforce Solutions with a human touch.

EEO Employer

LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.

This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.