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Staff Analog IC Design Engineer
2 weeks ago
Join us as an analog and mixed-signal design engineer in the PLL design team. Our designs enable the next generation of datacenters, automobiles and communications networks. You will work on system-level and circuit-level PLL design in the latest FINFET CMOS technology nodes.
PLL designs will support high-speed Serdes designs including PCI-Express, Ethernet, CPRI, and other applications at rates up to 112Gbps, 224Gbps and beyond.
Circuit-level PLL design and PLL top-level modeling and simulationDesign of analog circuits such as VCOs, charge pumps and voltage regulators
Custom circuit design in deep-submicron and FINFET CMOS technologies
Design of high-speed digital circuits such as dividers and clock distribution paths
MSEE with 2+ years or PhD with 1+ year experience in CMOS analog and mixed-signal circuit design
Detailed knowledge of PLL loop operation and design
Previous design experience of PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers
Design experience in deep-submicron and FINFET CMOS technologies
Knowledge of digital timing in PrimeTime and/or Nanotime is an asset
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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