Senior Software Engineer — SmartHLS Applications

Senior Software Engineer — SmartHLS Applications (FPGA/SoC) Join to apply for the Senior Software Engineer — SmartHLS Applications (FPGA/SoC) role at Microchip Technology Inc. Job Description Role Summary: Design, productize, and support SmartHLS-based C++ open-source libraries and reference applications for Microchip’s PolarFire® FPGA and PolarFire® SoC families. This role blends hands‑on feature development, on‑board test/CI bring‑up, developer‑experience tooling, and FAE/customer training. Collaborate with the HLS compiler team, CI/SQA, and FAE teams to deliver high‑quality, well‑documented IP and examples that accelerate customer adoption. About The Team The SmartHLS Applications team builds reusable C++ libraries (e.g., Vision, DSP, Math, etc.) and designs, integrates them with Libero® SoC, and maintains on‑board/CI testing to ensure reliability across supported boards (BeagleV‑Fire, Icicle, PolarFire Video Kit, Discovery Kit, …). The team also authors hands‑on labs and training materials for FAEs and customers. Key Responsibilities Build and maintain SmartHLS C++ libraries and examples Own feature development and pull requests in internal GitHub repositories Deliver production‑quality HLS IP, including verification, QoR analysis, and demo integration Develop and deliver FAE/customer training (labs, docs, IDE walk‑throughs), including Embedded SW, HLS, and System‑level flows Stand up and improve on‑board/CI testing for SmartHLS (for Windows and Linux); triage failures and drive fixes with CI owners Operate and enhance a board‑farm manager to reduce board contention and improve reservation/health checks of the hardware boards Support cross‑team handoffs by aligning deliverables and follow‑ups with internal and external customers Requirements / Qualifications Minimum Qualifications Bachelor’s or Master’s degree in Computer Science, Software Engineering, or related field 5+ years of professional experience in software development Strong modern C/C++ and Python programming skills Working knowledge of FPGA/SoC design flows Experience authoring training and developer guides (step‑by‑step labs & documentation) Hands‑on with FPGA development boards Git/GitHub development with pull‑request workflows for internal/external repositories Preferred Qualifications Familiarity with RISC‑V is a plus Experience using Generative AI tools and frameworks such as LLMs & RAGs Familiarity with High‑Level Synthesis Tools & Technologies Libero® SoC 2025.1, SmartHLS C/C++, Python, GenAI frameworks Jenkins, Confluence, Jira, Bitbucket, GitHub Linux and Windows development environments RISC‑V (Soft Mi‑V) reference platforms and evaluation boards Work Model Hybrid – Primary work location is Toronto, Ontario. The team collaborates in person for select planning, workshops, or lab activities; remote work is supported for focused development. Travel Time 0 % – 25 % Pay Range The annual base salary range for this position is $86,000 – $186,000. If you have any questions about pay or benefits, you can find more information at the link provided on the company career site. Ontario Accommodation In accordance with applicable laws (including human rights and accessibility legislation in Ontario), accommodation will be provided in all parts of the hiring process. Let us know what type of accommodations you require to help remove barriers so that you can participate throughout the interview process. This contact information is for accommodation requests only and cannot be used to inquire about the status of applications: * The base salary may vary based on location, experience, and other factors. #J-18808-Ljbffr