Layout Design Methodology, Staff Engineer in Da Nang

Location: Da Nang – (Onsite/Hybrid) Role Overview We are looking for a highly skilled Layout Design Methodology Engineer with a strong foundation in IC layout fundamentals and deep understanding of foundry design rules. In this role, you will drive the development and deployment analyzing robust layout methodologies that ensure high‑quality, manufacturable designs. Your work will require solid knowledge of device behavior, circuit‑layout interaction, and the impact of layout on performance, power, and long‑term reliability. A key part of this position is the ability to develop and apply layout automation tools —ranging from scripting-based verification automation to layout productivity tools, template generators, constraint‑driven automation, and intelligent QA flows. You will work closely with global teams and foundries to resolve design‑rule issues, perform sign‑off checks, prepare tapeout packages, and contribute to methodology and automation improvements. Strong English communication skills are essential for collaborating with international partners, foundries, and EDA vendors. Key Responsibilities Analog Mixed Signal Layout Design & Sign‑off Demonstrate in-depth knowledge of IC layout principles including matching, symmetry, common‑centroid, shielding, noise mitigation, EM/IR, ESD/latch‑up awareness. Apply a comprehensive understanding of foundry DRC/LVS/ERC/ANT/DFM rules to ensure full compliance while optimizing manufacturability, performance, and yield. Perform and analyze sign‑off checks: DRC/LVS/ERC/ANT/ESD/DFsingle ; debug with schematic, design, and PD teams. Prepare release/tapeout packages: GDS/OASIS, LEF/DEF, abstracts, waiver documentation, ECO tracking, sign‑off reports. Layout Automation & Productivity Tools (Enhanced & Expanded Section) Automation Development നമ്പ Develop and maintain automation scripts/tools using Python/Tcl/Perl/SKILL/Shell for: Auto‑naming conventions, versioning, and ECO tracking QA checks, checklist enforcement, quality metrics generation Build and enhance layout productivity tools , such as: Constraint‑driven placement/routing helpers Schematic‑layout consistency tools Contribute to internal layout automation framework , methodology improvement, and tool integration. Work with EDA vendors to evaluate, benchmark, and adopt new automation capabilities. Cross‑functional Collaboration Collaborate with design, AMS verification, CAD, and PD teams to resolve rule violations and methodology issues. Mentor junior engineers in'encache? layout techniques, scripting, and automation best practices. Present technical reviews, progress updates, and sign‑off reports to global teams. Requirements Must‑have媽媽 Experience: 3–8+ years in IC Layout/Physical Design with successful tapeouts. EDA Tools: Cadence Virtuoso (L/XL/GXL), Innovus / Synopsys CC /ంట్ICC2; Mentor/Siemens Calibre (DRC/LVS/DFM). Foundries: Hands‑on experience with TSMC/Samsung/UMC/GlobalFoundries PDKs. Layout Automation: Strong experience with Python/Tcl/Perl/SKILL and shell scripting Proven ability to automate verification flows, QA steps, accent, naming, constraint checks, and layout productivity tasks. QA Flow: Solid understanding of sign‑off flow, waiver handling, and quality tracking. English: Excellent written and spoken English for technical communication. Strong understanding of matching, shielding, symmetry, EM/IR, ESD/latch‑up, noisecreens, and analog/digital layout fundamentals. Ability to work independently and collaborate effectively across teams. Nice‑to‑have Experience in hierarchical/top‑level integration, LEF/DEF, abstract generation. Knowledge of PPA optimization, congestion mitigation, power grid design, and clock routing. AMS co‑simulation, PEX‑aware sign‑off, noise/linearity checks for mixed‑signal designs. Experience building automation frameworks . Multiple tapeouts; contributions to methodology or internal tools. Familiarity with Jira/Confluence, Git, CI/CD workflows for automation and traceability. #J-18808-Ljbffr