UFS IP Validation Engineer

Be among the first 25 applicants. Base pay range CA$70.00/hr - CA$90.00/hr Manager ( USA and Canada Staffing / Recruitment ) - Semiconductor / VLSI / EDA / Embedded Job Title – UFS IP Validation Engineer / Flash Memory Validation Engineer Project Duration – 12 Months + Chances of its further extension Job Description – Top 3‑5 Must Have Skills for this role: Hardware IP knowledge of storage devices including UFS, NAND, NOR, ePROM , etc SoC and Computer architecture Lab equipment, analyzers and hardware debugging techniques Key Responsibilities Participate in systems design development throughout the entire product lifecycle, from pre‑silicon and emulation through post‑silicon and software integration and validation. Lead technical presentations, demonstrating a good understanding of hardware architecture and expertise in systems design. Collaborate with Design, Software, Tools and other teams to drive the definition of testing and debug methodologies to provide the best possible coverage and customer experience for the UFS IP. Work with Program Leadership team to define the end‑to‑end plan and highlight possible risk areas and address concerns during planning. Be a leader and mentor to the operation team; be hands‑on and lead by example. Isolation and debug of issues found in the southbridge and peripherals during pre‑silicon, bring‑up, validation, and production phases of S3 products. Proactively support team culture that fosters knowledge sharing, excellence, and collaboration. Define and execute validation strategies, enablement of features and unit test plans. Publish and align test plan requirements, deliverables and dependencies. Work closely with supporting teams such as design, diagnostics, Software/Firmware/BIOS/driver, and project leadership. Lead cross‑functional technical discussions to drive root cause identification and resolution on technical issues. Drive and participate in technical innovations to enhance validation capabilities, including tool and script developments, technical and methodology enhancements. Requirements Knowledge of UFS standard and architecture, with encryption technology preferred. In‑depth knowledge of SOC architecture and concepts. In‑depth knowledge of southbridge technology. Experience with FPGA and other hardware emulation platforms for pre‑silicon debug. Strong understanding of BIOS, OS (Windows/Linux ), and driver‑level interactions and common failure points. Good understanding of Boot Flows/Sequences. In‑depth knowledge of system peripherals such as PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART and other data bus connections. Experience with the UFS analyzer/exerciser, common lab equipment, computer hardware, and networks. Led process improvement initiatives to improve engineering quality. Strong technical leadership and mentoring skills. Knowledge of standard power management features and use‑cases. Preferred Experience Minimum 3‑6 years of experience in pre and post‑silicon validation and 4‑8 years experience in semiconductor industry. Demonstrated ability to grasp new technical concepts quickly. Experience with IP/System level bring‑up , SOC debug techniques and methodologies. Strong analytical/problem solving skills and pronounced attention to details. Excellent written and verbal communication skills. Self‑starter, strong collaborator, and able to independently drive tasks to completion. Strong organizational skills and ability to handle multiple issues at the same time. Academic Credentials Bachelor’s/Master’s degree in Computer Engineering, Electrical Engineering or related field strongly preferred. Seniority level Mid‑Senior level Employment type Contract Job function Semiconductor Manufacturing #J-18808-Ljbffr