Formal Verification Engineer

2 days ago


Markham, Canada Mindlance Full time

Top 3-5 must have skills: Experience with System Verilog Assertions, SystemVerilog / Verilog VCS/DVE familiarity is necessary and experience with formal tools like VC-Formal/Jasper Test plan execution, development, and debug testbench and/or design issues using formal tools and provide feedback for design improvements Knowledge of scripting languages like Python and Tcl The Role: The GMHUB team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced ASIC Design Verification engineer, who will be involved in different aspects of verification activities with focus being formal verification. The candidate will manage/utilize a variety of verification components, methodologies (formal/simulation) to ensure the robustness of RTL designs. This role offers you the chance to work with some of the most talented verification experts in the industry, applying cutting‑edge verification techniques to verify our complex designs. The Person: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem‑solving skills, attention to detail and willing to learn and ready to take on problems. Responsibilities: Drive formal verification execution with support from FV and design leads. Collaborate with design and architecture teams to understand design specifications and develop verification requirements. Debug testbench and/or design issues using formal tools and provide feedback for design improvements. Responsible for verification quality metrics like pass rates, code/functional coverage and proof convergence. Document Formal Verification processes. Continuously learn and stay ahead of the curve in verification in general and formal in particular. Preferred experience: Successful candidate should possess the following personal qualities and technical skills: Experience with System Verilog Assertions, SystemVerilog / Verilog is a must Strong understanding OOP and UVM is a huge asset. Experience with Low Power Verification and debug methodology is a plus VCS/DVE familiarity is necessary and experience with formal tools like VC-Formal/Jasper is a huge plus. Knowledge of scripting languages like Python and Tcl is plus. EEO: “Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.” #J-18808-Ljbffr



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