Principal Test Engineer

Inpho is a fast-growing startup, focused on developing cutting‑edge optoelectronic solutions for next‑generation communications, and photonic systems. Our multidisciplinary team is pushing the boundaries of innovation in integrated photonics and semiconductor packaging. Inpho’s new class of electro‑photonic chips is poised to revolutionize and disrupt the optical interconnect market. Utilizing this new class of chips enables existing optical interconnect systems to be built at much lower cost, new architectures to be deployed that provide significantly higher price / performance, and a whole new generation of higher speed interconnect to be built that to date have been impossible. About the Role We’re looking for a Principal Test Engineer to join our NPI Engineering team. Reporting to the VP Engineering, New Product Development, this critical role will lead the development, implementation, and optimization of production high volume test solutions for a new class of high performance electro‑optical designs. This role requires strong technical expertise in ATE development, test architecture, DFT integration, high performance hardware design, and a passion for building robust, scalable, and cost‑effective test solutions. This is a unique opportunity to trailblaze next‑generation test solutions for a new class of high performance electro‑optical designs. The successful candidate will be responsible for developing test and characterization platforms, to ensure Inpho’s cutting‑edge products are delivered with high quality. Key Responsibilities Test Development & Implementation – 40% Architect test solutions (platform, hardware and software) for high‑volume manufacturing of very high‑speed products optimizing for precision, repeatability and scalability. Develop ATE test programs (wafer and final test) for electronic and electro‑optical high‑speed analog semiconductors. Oversee third‑party partners and suppliers in the development and deployment of test solutions. Collaborate with Product Engineering to define test plans, validate test coverage, and ensure correlation with bench measurements. Define and develop hardware (load boards, probe cards) with a focus on signal integrity and high‑speed precision analog measurements. Product Bring‑Up & Characterization and Qualification Support – 20% Work with Design and Product Engineering to validate test program functionality, debug issues, and correlate with design targets. Develop qualification and characterization solution (HW and SW) for NPI. Assist in parametric characterization across PVT (process, voltage, temperature) to establish robust production limits. Develop and automate characterization routines and tools to streamline data collection and analysis. Yield, Cost, and Quality Optimization – 20% Drive continuous improvement of test programs for yield enhancement, test time reduction, and test cost optimization, while maintaining outgoing quality. Support GR;R analysis, test limit optimization, and identification of systematic test escapes or false failures. Implement outlier screening and guard banding strategies in collaboration with the Product Engineering team. Cross‑functional Collaboration – 15% Partner closely with Product Engineering, Design, Quality, and Operations teams to ensure seamless integration of test into the overall product lifecycle. Engage early in the design cycle to influence testability architecture and DFT adoption. Coordinate with OSATs and internal test teams on test correlation, hardware deployment, and issue resolution. Provide ongoing support for high‑volume production, including test program maintenance, production issue debug, etc. Support root cause analysis of test‑related field returns or yield excursions and implement corrective actions in test flows. Support supplier assessment, selection and qualification to ensure successful test deployment. Qualifications BS or MS in Electrical Engineering or related field. (Ph.D. is an asset.) 9+ years of experience in test development for analog, mixed‑signal, or high‑speed ICs. Experience architecting complex test solutions optimized for yield, test time and signal integrity. Solid understanding of analog, RF, or high‑speed test techniques (e.g., ADC / DAC, PLLs, TIA / laser drivers). Hands‑on experience with test hardware design (load boards, socket / probe card design, signal integrity). Deep experience with ATE platforms (Advantest 93K, Teradyne UltraFlex, etc.). Strong programming and automation skills (C / C++, Python, Java, etc.). Proficient in data analysis using tools (e.g. JMP, Python, MATLAB, etc.). Familiarity with DFT and FMEA methodologies, including integration with design and product engineering workflows. Preferred Experience Familiarity with signal integrity, high‑speed measurements, and S‑parameter analysis. Experience supporting yield ramp, test cost reduction, and volume manufacturing at OSATs. Experience using simulation or modeling tools for test coverage analysis or ATE correlation. Why Join Inpho? Be part of a mission‑driven startup shaping the future of photonics. Collaborate with top researchers and engineers in a dynamic, innovation‑driven environment. Contribute to building a lab from the ground up and influencing technical infrastructure. Competitive salary and equity packages, flexible work environment, and career growth opportunities. #J-18808-Ljbffr