FPGA RTL Design Engineer
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Develop FPGA and CPLD architectures with customers and Fidus teams Implement RTL, integrate IP, simulate designs, and close timing Conduct design reviews against requirements and quality standards Test and debug prototypes in the laboratory Author test plans, design descriptions, and user documentation Requirements:
Minimum five years designing FPGAs with RTL, Verilog, or VHDL Experience with Xilinx or Altera families and tool flows Knowledge of SystemVerilog, Vivado, Quartus, or ModelSim Experience with verification, test benches, simulations, and timing closure B.A.Sc., B.Eng., or equivalent degree and fluent English Apply FPGA architecture, RTL implementation, verification, and timing closure skills to complex client systems at Fidus.
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