Senior ASIC Design Verification Engineer, Compute DSP/AI Processors

2 days ago

Winnipeg, Manitoba, Canada MaC VC Full-time
Company Qualcomm Canada ULC

Job Area Engineering Group, Engineering Group > ASICS Engineering

General Summary Do you ever wonder when connected devices become thinking devices? Be part of the group that is working on technology that will bring “Cognition” to all connected devices: That means devices that don’t just react to their surroundings, they interact with the world.

We are a compact, tightly knit ASIC IP team of architects, design, and verification engineers. We create HW IP in the heart of the Snapdragon DSP Neural Processing Unit (NPU) that works in coordination with the other NPU components to accelerate AI machine learning, video and other dsp applications. We’re continuously evolving and improving our design and verification architectures to tackle complex engineering problems. To achieve the high standards of Qualcomm products, our team members contribute with a variety of skills and participate in many aspects of the design, verification, and final product evaluation processes.

We are looking for few good ASIC Design Verification Engineers to be part of our team to innovate and design leading edge Qualcomm Snapdragon DSP processors that will empower AI and video processing applications and products. We are open to all levels of applicants; the role (Jr, Sr., Staff) and responsibility will be commensurate with experience.

As Part Of Our Team Your Responsibilities Would Include

Verification of a complex IP block using UVM methodology

Resolving architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision

Collaborating closely with the Design team to test, debug and close coverage on the design

Modifying testbench components such as scoreboard, agents, sequences, to verify new features

Writing tests in SystemVerilog

Writing functional coverage and assertions using SystemVerilog

Regression maintenance and triaging of test failures

Contributing to testbench architecture and optimization

Contributing to testplan implementation and verification methodology

Supporting integration testing of the design

Performance testing

Qualifications

Strong problem solving and analytical thinking skills

Excellent communication skills

Self-motivated, goal oriented, team player

New Grad

Bachelors - Engineering, Computer Engineering

Understanding of digital logic

Understanding of objected oriented programming concepts

some design or DV experience, whether in work, co-op, or coursework

Senior Or Above

2+ years of direct experience in ASIC verification

Experience with verification methodology (UVM, assertions, coverage-driven constrained-random verification)

Experience with scripting languages (Python, CShell)

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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