Digital ASIC Verification And RTL Engineer
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Define architectures and specifications for digital IC blocks Develop RTL models and verification environments Perform synthesis, timing closure, and gate-level simulation Generate vectors and support lab testing Document designs and execute incremental maintenance updates Requirements:
BSc or MSc in Electronic Engineering or Computer Engineering Three to six years of digital IC design experience VHDL or Verilog design and simulation experience Synopsys, Cadence, or Mentor front-end flow experience Hands-on csh, Tcl/Tk, or Perl scripting experience Bring RTL, verification, synthesis, simulation, and scripting capabilities to StarIC’s digital integrated circuit development work.
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