Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences – from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE: 

The Data Accelerator (DACC) team at AMD is seeking an ASIC Design Verification Engineer who will be involved in multiple aspects of IP verification. This role is an excellent opportunity to work on next generation technologies that are part of AMD ASICs powering Servers, AI, Client and Embedded markets. You will join one of the fastest-growing areas of  adding custom hardware offload engines to support complex operations like encryption, authentication, compression, GPU/CPU compute offloads & virtual machines live migration. This is a tremendous opportunity to get in early into the rapidly expanding domain of custom hardware accelerators. The Design Verification (DV) group within this team is responsible for developing a scalable DV flow and environment with emphasis on automation (using AI), power and performance verification (PPV) and emulation support. Our management fosters and encourages continuous technical innovation to showcase success as well as continuous career development.

THE PERSON:

Highly skilled in advanced ASIC Functional Verification techniques and planning. Eager to learn new designs and implementation techniques.  Enjoys an environment where everyone in the team can grow and develop with a sense of global team spirit. Strong analytical thinking and problem-solving skills, excellent attention to detail. 

KEY RESPONSIBILITIES:

• Develop and maintain block level IP verification testbenches, test methodology and infrastructure
• Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
• Actively drive Unified Test Plan (UTP) with sub-system, emulation and Soc teams.
• Debug and solve issues with SoC Integration and SoC DV teams
• Deploy industry leading verification methodologies such as UVM, formal verification etc.
• Take end to end ownership of key features for the projects
• Reproduce silicon functional bugs in simulations and/or formal verification tools
• Conduct and participate in code reviews

PREFERRED EXPERIENCE: 

• Extensive hardware verification experience
• Must be proficient in Verilog, System Verilog, C and C++, UVM, and working in Linux and Windows environments
• Must have ASIC design knowledge and be able to debug RTL code using simulation tools
• Must have excellent programming skills
• Must have exposure to Makefile, scripting languages like perl, python, ruby etc. and use of AI.

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering 

LOCATION:  Markham, ON

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.