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High Level Synthesis Compiler Engineer
3 weeks ago
About Us
Altera is at the forefront of hardware acceleration, building innovative solutions for next-generation systems. We are seeking a highly skilled Senior HLS Compiler Engineer to join our team. This role is critical in advancing our high-level synthesis (HLS) compiler stack.
Responsibilities
Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang.
Architect and implement new compiler passes, analyses, and code transformations to improve synthesis quality and performance.
Collaborate with hardware and software teams to define and implement new language features and optimizations.
Mentor junior team members and drive best practices for high-quality, maintainable code.
Contribute to open-source projects and stay current with advancements in the LLVM/MLIR/Clang ecosystems.
Analyze and optimize the compilation flow from C/C++/SYCL to hardware description languages.
Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position's location, as well as the candidate's experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.
Estimated Salary Range: $139,000 – $201,250 CAD
We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not for this role.
Qualifications:Required Qualifications
Bachelor's, Master's, or Ph.D. in Computer Science, Electrical Engineering, or related field.
5+ years of experience developing compilers, with a strong background in HLS flows.
Extensive hands-on experience with MLIR and Clang/LLVM internals.
Proficiency in C++ (modern standards), with a strong software engineering foundation.
Deep understanding of compiler design, optimization techniques, and code generation.
Demonstrated experience in HLS toolchains, especially the lowering of high-level languages to hardware.
Experience with parallelism, pipelining, and hardware resource optimization in compilers.
Preferred Qualifications
Contributions to MLIR or Clang open-source projects.
Experience with Verilog/VHDL or other hardware description languages.
Knowledge of high-level hardware programming models (e.g., SYCL, OpenCL, CUDA).
Familiarity with FPGA or ASIC design flows.
Strong communication skills and experience working in cross-functional teams.
