Principal Engineer Memory Test and BIST

Our client is a global frontrunner in semiconductor manufacturing, delivering advanced chip fabrication services to leading technology companies around the world. Known for its pioneering process technologies and unmatched high-volume production capabilities, the company plays a vital role in driving innovation across sectors—from consumer electronics and mobile devices to artificial intelligence and beyond. Its unwavering commitment to quality, operational efficiency, and environmental sustainability positions it as a foundational pillar of the modern electronics ecosystem.

The job
We are seeking a highly experienced and exceptionally skilled Senior Technical Manager, Design for Test (DFT) and Memory Built-In Self-Test (BIST) to join a world-class team. This is a critical technical leadership role for a 'Memory Guru' who will drive innovation and solve complex, unprecedented challenges in cutting-edge memory technologies.

This role is paramount to the company's strategic initiatives, especially in the context of the AI and Machine Learning boom, where merging logic and memory for energy-efficient, high-bandwidth solutions is a key bottleneck. The ideal candidate will be a visionary who can control BIST DFT architecture, develop silicon-proven custom BIST solutions for emerging memories, and ensure "first-time-right" silicon on process technologies never used before.

You will leverage your 10+ years of extensive experience in memory testing and self-testing, with a proven track record in advanced memory test algorithms, defect modeling, and state-of-the-art design-for-test methodologies. This position demands a deep understanding of memory circuit design, ASIC design, Compute-in-Memory (CIM), chip design and 2.5D + 3D System-in-Package architectures, coupled with hands-on expertise in EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens) and the ability to interact effectively with EDA vendors.
You will play a pivotal role in ensuring the quality and reliability of our memory technologies, collaborating with cross-functional teams in Canada and globally (Asia, Europe R&D, product, process, and reliability engineering teams) to drive innovation and deliver cutting-edge solutions that enable tens of billions of end products worldwide.

You are a Semiconductor Expert who has achieved:
10+ years of extensive, hands-on experience in memory test and memory self-test development, with a proven track record as a "Memory Guru."
Demonstrated expertise in advanced memory test algorithms and design for test (DFT), with a focus on problem resolution and preventing escapes.
Significant experience in memory defect and fault modeling, failure analysis, and debugging complex silicon issues.
Deep understanding of memory circuit design principles and methodologies, with prior hands-on experience that allows for effective interaction with designers.
Expert proficiency in EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens, Cadence) and proven ability to develop custom BIST solutions.
Strong knowledge of ASIC design, chip design, and integration, particularly concerning memory subsystems and logic-memory interaction.
Proactive problem-solver with exceptional resilience, initiative, and the ability to tackle novel, undefined problems in cutting-edge technology.
Excellent negotiation skills for interacting with EDA vendors on new processes and tool requirements.
Strong written and verbal communication skills, capable of concise technical communication across global teams.

Preferred Qualifications:
Advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, or a related field.
Experience with memory technologies such as HBM memory controllers, RRAM, MRAM or emerging memory.
Familiarity with advanced semiconductor manufacturing processes and technologies.
Active participation or interest in industry standards bodies (e.g. IEEE) or technical conferences (e.g., ITC).
Experience or strong interest in project and technical team management.

Interested?
Contact Anton van Rossum at or

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