Asic design lead

About O-HIVE ASIC Design Lead
Company: O-HIVE Inc.
Location: Windsor, Ontario, Canada
Employment Type: Full-Time
Department: Semiconductor Engineering / AI Hardware
Seniority: Senior / Technical Lead
O-HIVE is an AI and spatial vision technology company developing Visual Language Model (VLM)-powered solutions for industrial automation, robotics, autonomous systems, and intelligent vision applications.
Our technology enables machines to perceive, understand, and interact with physical environments through advanced computer vision, spatial intelligence, and edge AI.
We are expanding our semiconductor development capabilities to build a next-generation Spatial Vision Intelligence Chip (SVIC) , an ultra-compact, power-efficient ASIC designed to accelerate visual perception, object detection, spatial mapping, pose estimation, navigation, and VLM inference.
Our targeted semiconductor architecture uses advanced 4 nm process technology and integrates dedicated AI accelerators with programmable FPGA components and embedded processing capabilities.
Role Overview We are seeking an experienced and hands-on ASIC Design Lead to lead the architecture, RTL development, verification, and implementation of O-HIVE's next-generation spatial vision and AI inference accelerator.
The ideal candidate has extensive experience in digital ASIC design, So C architecture, FPGA prototyping, and semiconductor development, with the ability to translate complex AI and computer vision algorithms into efficient hardware implementations.
This role will take technical ownership of the ASIC development lifecycle, from initial architectural specifications and microarchitecture design through RTL implementation, functional verification, physical design coordination, tape-out, and silicon validation.
The ASIC Design Lead will collaborate closely with AI researchers, VLM engineers, FPGA engineers, system architects, and semiconductor manufacturing partners to develop a highly integrated, low-power AI processor for robotics, autonomous navigation, industrial inspection, and embedded vision applications.
Key Responsibilities1. ASIC Architecture & Microarchitecture Lead the definition and development of digital ASIC architecture for spatial vision intelligence and edge AI acceleration.
Translate AI, computer vision, and spatial perception workloads into hardware architectures suitable for ASIC implementation.
Design specialized accelerators for feature extraction, visual mapping, pose estimation, object detection, navigation, and VLM inference.
Define datapaths, memory hierarchies, processing pipelines, interconnects, and hardware interfaces.
Develop microarchitecture specifications, functional block diagrams, and detailed design documentation.
Evaluate design tradeoffs involving performance, power consumption, silicon area, memory bandwidth, and implementation complexity.
Work with AI engineering teams to optimize neural network computation, quantization, and hardware inference efficiency.
2. RTL Design & Development Lead and perform RTL design using System Verilog and Verilog.
Develop synthesizable RTL modules for AI accelerators, control logic, memory interfaces, and high-performance processing engines.
Design and integrate reusable RTL IP blocks.
Implement efficient pipelined, parallel, and low-power processing architectures.
Perform RTL code reviews, design optimization, and technical debugging.
Establish RTL coding standards, design methodologies, and version-control practices.
Ensure design compatibility with synthesis, verification, and downstream physical implementation requirements.
3. Functional Verification & Validation Develop comprehensive ASIC verification strategies and test plans.
Lead simulation-based verification using System Verilog, UVM, and industry-standard verification tools.
Implement testbenches, assertions, coverage models, and regression testing environments.
Perform functional verification, formal verification, and equivalence checking where appropriate.
Identify and resolve RTL functional defects and integration issues.
Coordinate clock-domain crossing, reset-domain crossing, and timing-related verification.
Establish verification sign-off criteria before physical implementation and tape-out.
4. Physical Design & Tape-Out Coordinate ASIC implementation activities, including logic synthesis, floorplanning, placement, clock-tree synthesis, routing, and timing closure.
Work with internal engineers and external semiconductor partners to meet power, performance, and area (PPA) targets.
Support static timing analysis, power analysis, design rule checking, and layout-versus-schematic verification.
Coordinate design-for-test (DFT) planning, scan insertion, ATPG, and manufacturing test readiness.
Support advanced-node semiconductor development, targeting 4 nm process technology.
Manage design readiness, engineeri