Fpga Senior Designer
4 days ago
montréal, québec, Canada
Amaris Consulting
Full-time
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4 days ago Be among the first 25 applicantsWe are looking for aSenior FPGA Designerto join a team building the next generation ofwireless ASICs and So Cspowering products such as audio headsets, speakers, mice, proximity detection, ranging, and Io T devices.
In this role, you willlead the design and implementation of complex digital circuitswithin ASICs—covering architecture definition, RTL coding, synthesis, timing analysis, and close collaboration with verification and physical design teams. You will own critical design blocks or subsystems, ensure performance and power efficiency, and mentor junior engineers.
Missions & ResponsibilitiesDefine ASIC architecture: functional blocks, data paths, and interfaces (performance, area, and power tradeoffs).
Write high-qualityRTL code(Verilog, System Verilog, VHDL) that is maintainable and spec-compliant.
Performsynthesisandstatic timing analysis (STA) , resolving timing-critical paths and optimizing llaborate with verification teams: provide documentation, testbench support, and debugging.
Guide and review the work of digital designers, ensuring quality standards.
Applypower-aware design techniques(clock gating, power domains, leakage reduction).
Work with the physical design team on constraints, layout reviews, and timing issues.
Take ownership of assigned design blocks/subsystems, ensuring timely ntribute to design reviews and lead digital validation ntor and
In this role, you willlead the design and implementation of complex digital circuitswithin ASICs—covering architecture definition, RTL coding, synthesis, timing analysis, and close collaboration with verification and physical design teams. You will own critical design blocks or subsystems, ensure performance and power efficiency, and mentor junior engineers.
Missions & ResponsibilitiesDefine ASIC architecture: functional blocks, data paths, and interfaces (performance, area, and power tradeoffs).
Write high-qualityRTL code(Verilog, System Verilog, VHDL) that is maintainable and spec-compliant.
Performsynthesisandstatic timing analysis (STA) , resolving timing-critical paths and optimizing llaborate with verification teams: provide documentation, testbench support, and debugging.
Guide and review the work of digital designers, ensuring quality standards.
Applypower-aware design techniques(clock gating, power domains, leakage reduction).
Work with the physical design team on constraints, layout reviews, and timing issues.
Take ownership of assigned design blocks/subsystems, ensuring timely ntribute to design reviews and lead digital validation ntor and