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Digital Signal Design Engineer
3 weeks ago
About Us
Synopsys, Inc. is a leader in the innovations that change the way we work and play.
We are powering the Era of Smart Everything with the world's most advanced technologies for chip design and software security.
Job Description
As an analog and mixed-signal design engineer in the PLL design team, you will work on system-level and circuit-level PLL design in the latest FINFET and gate all around CMOS technology nodes.
You will be responsible for designing high-speed SerDes blocks and PLL circuit components such as VCOs, charge-pumps, regulators, and high-speed dividers.
The designs will support rates up to 112Gbps, 128Gbps, 224Gbps and beyond.
Responsibilities
- Circuit-level PLL design and PLL top-level modeling and simulation
- Design of analog circuits such as VCOs, charge pumps, and voltage regulators
- Custom circuit design in deep-submicron and FINFET CMOS technologies
- Design of high-speed digital circuits such as dividers and clock distribution paths
- Schematic entry and spice simulation of custom circuits
- Provide mentoring and technical leadership to junior designers
- Coordinate and interface with layout and CAD teams
Requirements
- 8+ years of experience within CMOS analog and mixed-signal circuit design with MSEE or PhD
- Detailed knowledge of PLL loop operation and design
- Experienced in design of SerDes blocks and/or PLL circuit components
- Design experience in FINFET and gate all around CMOS technologies
- Hspice, Finesim, PrimeSim or similar spice-type simulators
- Schematic entry in Synopsys Custom Designer or similar tools
- Knowledge of digital timing in PrimeTime and/or Nanotime is an asset
