Principal Analog Methodology Engineer
2 weeks ago
Synopsys' broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems.
Our Solution IP GroupWe are ramping up high-performance computing (HPC) demand and looking for an enthusiastic applicant to join our team. As a member of our cross-functional team of analog and mixed-signal circuit designers, you will work on design and methodology, requiring hands-on experience with transistor-level simulations, reliability analysis, static timing analysis (STA) tools, and a deep understanding of silicon IP release requirements.
Key Responsibilities- Design and develop high-performance computing analog IP.
- Collaborate with a cross-functional team of analog and mixed-signal circuit designers.
- Work on design and methodology, requiring hands-on experience with transistor-level simulations, reliability analysis, and static timing analysis (STA) tools.
- Develop and maintain automation scripts to streamline design flows.
- Lead and train junior engineers to become experts with new methodologies.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar technical field.
- BSEE degree and 18-25 years of experience in IC design, or MSEE (or PhD) with 15-18 years of experience.
- Extensive programming skills in languages such as Python, Perl, TCL, and C/C++.
- Ability to provide automation for rapid and dynamic design needs.
- Extensive knowledge of Analog & Mixed-Signal circuit design.
- Direct design experience in high-speed PHY such as SERDES, DDR, or HBM is a strong plus.
- Proficiency with spice simulators including HSPICE, PrimeSim/FineSim, and XA.
- Deep knowledge on DC/AC/Transient, Cross corners PVT, Static & Dynamic CCK, Equivalency checks, Aging, EMIR/SHE Reliability analysis, and Monte Carlo simulations.
- Understanding of behavioral Verilog models & experience in SystemVerilog for AMS circuits.
- Prior experience on products/test chips bring up, lab debug, and simulations to silicon correlation is highly desirable.
- Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart.
- Candidate with Machine Learning paradigms/techniques understanding with knowledge of applying it in modeling, circuit design flow & simulations is desirable.
If you require an accommodation, please contact hr-help-canada@synopsys.com
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