Analog Design Engineer
6 days ago
Microchip Technology is seeking an experienced Analog Design Engineer to join our team. As a key member of our Timing and Communication Group, you will be responsible for designing, simulating, and validating analog integrated circuits (ICs) for our mixed signal SOC designs.
The Analog team at Microchip develops critical IP blocks used in our TCG timing products. These circuits include multi-GHz PLL circuits, high-speed digital circuits, MEMS drivers, and high-speed performance IO pads. As an Analog Design Engineer, you will work with our analog design lead and architects to design specific analog IP blocks, simulate analog circuits across process corners and operating conditions, and model design blocks to be included on top-level mixed signal simulations.
We are looking for a highly skilled and motivated individual with a strong background in analog design and a passion for innovation. If you have a Bachelor's or Master's degree in Electrical Engineering and a minimum of 1-2 years' experience as an IC layout designer using deep submicron CMOS process technology, we encourage you to apply.
Our company offers a total compensation package that ranks among the best in the industry, including competitive base pay, restricted stock units, and quarterly bonus payments. We also offer health benefits, retirement savings plans, and an industry-leading IESPP program with a 6-month look-back feature.
As a member of our team, you will have the opportunity to work on cutting-edge technology and collaborate with a talented group of engineers. If you are passionate about analog design and want to be part of a dynamic and innovative company, we encourage you to apply for this exciting opportunity.
Responsibilities:
- Design, simulate, and validate analog integrated circuits (ICs) for mixed signal SOC designs
- Work with analog design lead and architects to design specific analog IP blocks
- Simulate analog circuits across process corners and operating conditions
- Model design blocks to be included on top-level mixed signal simulations
- Block-level validation of process silicon devices and system-level lab evaluation
Requirements:
- Bachelor's or Master's degree in Electrical Engineering
- Minimum 1-2 years' experience as an IC layout designer using deep submicron CMOS process technology
- Knowledge of chip-level integration and ESD concepts is a plus
- Knowledge in scripting using SKILL language, Perl, and TCL is a plus
- Strong knowledge in Cadence IC layout flow and tools
- Familiar with Innovus, is a plus
- Experience in layout verification and debugging such as DRC, ERC, LVS, ANTENNA DRC
- Floor planning from sub-block to chip top level
- Very good understanding of matching techniques
- Knowledge in TCL, Perl, Python, and/or SKILL languages is a plus
- Good communication, teamwork skills, and experience working with multi-site teams desirable
Travel Time: 0% - 25%
Pay Range: $76,000 - $114,000
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