Verification Expert for Robust RTL Design
4 days ago
The Role:
We are seeking a highly skilled and motivated verification engineer to contribute to the success of our projects.
Key Responsibilities Include:
- Maintaining and enhancing verification environments to ensure the robustness of RTL designs.
- Triage and debugging regression results to identify areas for improvement.
- Analyzing test plan coverage to optimize verification efficiency.
- Writing test cases in SystemVerilog, UVM, and Ruby.
To be successful in this role, you will possess:
- Experience with SystemVerilog, Verilog, and C/C++ programming languages.
- A strong understanding of the UVM-based verification methodology.
- Familiarity with Low Power Verification and debug methodologies.
- VCS/DVE experience and ability to multitask.
We Offer:
A competitive salary range estimated at $110,000 - $140,000 per year.
Strong teamwork and communication skills are essential for this position.
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