Lead ASIC Verification Engineer for Mixed-Signal Design

1 day ago


Toronto, Ontario, Canada Renesas Electronics Full time

Renesas Electronics is seeking a highly skilled Lead ASIC Verification Engineer to join our team in Canada, preferably in Montreal, Ottawa, or Toronto.

About the Role

As a key member of our verification team, you will be responsible for improving and maintaining our UVM test environment, creating new test cases, and debugging mixed-signal chips in digital simulation. You will also lead the verification of small projects and mentor less experienced engineers.

Responsibilities
  • Verify mixed-signal ASICs in a SV UVM environment
  • Implement test cases based on functional specifications and test plans
  • RTL and possibly Gate level debug of mixed-signal ASICs
  • Implement functional coverage and aid designers in reviewing code coverage
  • Lead the verification of a small project
  • Mentor less experienced engineers
Qualifications
  • Bachelor's degree or equivalent technical degree in Electrical/Computer/Software Engineering
  • 8+ years of practical design verification experience using SystemVerilog UVM and ASIC verification
  • Experience with functional coverage driven verification sign-off
  • Experience contributing to verification plans
Preferred Skills
  • Knowledge of PLLs
  • Experience with Synopsys and/or Cadence simulation tools
  • Ability to work in a Unix/Linux operating system environment
  • Knowledge of scripting languages such as Python or equivalent
  • Experience with mixed-signal design modelling and debugging
Compensation and Benefits

The estimated salary for this role is $140,000 - $160,000 per year, depending on experience. We offer a comprehensive benefits package, including health insurance, retirement plan, and paid time off.

Please note that these details are subject to change and may not reflect the current market conditions.



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