Digital Verification Engineer

4 weeks ago


Markham, Ontario, Canada Synopsys, Inc. Full time
About the Role

We are seeking a highly motivated and innovative Digital Verification Engineer to join our team at Synopsys, Inc. As a key member of our mixed-signal design team, you will be responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

Key Responsibilities
  • Design and develop modular constrained-random Verilog and System Verilog testbenches and UVM/VMM testbenches
  • Execute system-level tests and validation in a prototype environment
  • Perform functional coverage, assertion coverage, and code coverage
  • Track issues in Jira and document in Confluence
  • Create and update test plans and test cases
  • Monitor simulation regressions and analyze failure cases
Requirements
  • Hands-on experience in writing test cases in Verilog and System Verilog
  • Basic understanding of assembly language programming and RISC processors
  • Familiarity with scripting languages (Python or Perl) and working in a Linux environment
  • Familiarity with VMM/UVM verification methodology
  • Familiarity with code quality metrics
  • Knowledge of high-speed digital & mixed-signal design is desired
  • Hands-on FPGA design and verification experience is desired
  • Familiarity with version control systems (GIT/SVN/Perforce) is an asset
About You
  • Highly organized and detail-oriented
  • Excellent communication skills
  • A proactive problem solver
  • A team player who thrives in a collaborative environment
  • Adaptable and eager to learn new technologies
About Synopsys, Inc.

Synopsys, Inc. is a leading provider of electronic design automation (EDA) software and IP solutions. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.



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