Digital Design Engineer

1 day ago

Ottawa, Ontario, Canada Marvell Technology Full time
About Marvell

Marvell's semiconductor solutions are the backbone of the data infrastructure that connects our world. Across enterprise, cloud, and AI, automotive, and carrier architectures, our innovative technology is driving new possibilities.

At Marvell, you can make a meaningful impact on the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to drive purposeful and enduring innovation, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Optical PHY BU develops cutting-edge optical Ethernet Transceiver ASICs. Current online working and meetings are based on cloud services. To respond to the dramatically increased demands of cloud-based connection capability, major cloud computing companies urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs.

As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams, and timing closure.

What You Can Expect
  • High-speed data path RTL implementation using Verilog, synthesis, and backend resources
  • Integrate vendor IP and support
  • Well-versed with the complete ASIC flow from micro-architecture to customer deployment
  • Post-silicon debug and correlation
  • Specify and implement digital features of a chip
  • Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross-clock domain (CDC) analysis, and functional verification
  • Develop ASIC specification and micro-architecture of signal processing and communications algorithms
  • Assist in design automation of various aspects of the CAD EDA flow
  • Mentorship of junior team members
What We're Looking For
  • Bachelor's, Master's, or PhD with minimum 8+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology
  • Experience of entire design cycle from micro-architecture specification definition, Verilog coding, synthesis, and timing closure to post-silicon debug and support in lab environment
  • Strong language user in Verilog, System Verilog, Perl, Unix Shell
  • Experience in both RTL development (block and subsystem level) and gate-level verification and debug
  • Hands-on experience with matching DSP block model functionality to RTL's, synthesis, static timing analysis, and functional verification
  • Strong design experience in high-speed DSP physical layer products
  • Experience with chip bring-up and functional validation of the product in the lab
  • Strong system-level modeling, debugging, and troubleshooting
  • Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
  • Effective communication and presentation skills
  • Team player

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