ASIC Digital Design Engineer
6 hours ago
At Synopsys, we're at the forefront of innovation, driving the Era of Smart Everything. Our Silicon IP business is revolutionizing the way we integrate capabilities into SoCs, offering the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
Join Our Expert TeamWe're seeking a highly skilled ASIC Digital Design Engineer to join our Solution Group, DDRPHY IP team. As a key member of our team, you'll play a crucial role in innovating and developing the latest world-class market-leading DesignWare DDRPHY IP solution.
Responsibilities:- Conduct low-power digital microarchitecture analysis, definition, and documentation
- Design, debug, and verify RTL logic for optimal timing, area, and power
- Lead power analysis flow, generate and analyze data for power and clock gating efficiency
- Drive efforts to reduce power and improve clock gating efficiency
- BS/MS in Electronics Engineering with at least 5 years of design experience
- Experience with synthesizable Verilog and System Verilog design concepts and implementation
- Front-end design flow expertise, including linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
- Excellent communication skills and self-motivation
- Understanding of DDR memory and DDRPHY architecture is a plus
If you're passionate about innovation and driven to make a difference, we want to meet you. Let's shape the future of Silicon IP together.
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