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Senior Design Verification Engineer

2 months ago

Markham, Ontario, Canada Synopsys Full time
Unlock Your Potential as a Design Verification Engineer at Synopsys

At Synopsys, we're driving innovation in the Era of Smart Everything. Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.

Join Our Team of Experts

We're seeking an experienced Design Verification Engineer to join our team. As a key member of our team, you'll be responsible for defining verification plans and building verification environments for IP level designs using System Verilog with UVM.

Key Responsibilities
  • Develop and implement advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification to achieve functional safety metrics for automotive applications.
  • Write test cases, checkers, and coverage that implement the verification test plan.
  • Provide technical leadership to junior engineers and interns.
Requirements
  • Bachelor's or Master's degree with 10+ years of digital verification experience in the industry.
  • RTL verification using coverage-driven verification techniques.
  • Scripting in any language, with programming experience or coursework in C, C++.
  • Proficient in HDL languages System Verilog, Verilog, or VHDL.
  • Good analytical, oral, and written communication skills.
  • Self-motivated, proactive team player.
What You'll Gain
  • Cross-functional learning and interaction with professional teams across domains and geographies.
  • Customer-facing role working in close collaboration with pre and post-sales teams.
  • Develop systematic ways to address new problems and think outside the box.
  • Have an impact on new product architectures, quality, and development strategies.