Formal Verification Engineer
6 days ago
We are seeking a highly skilled Formal Verification Engineer to join our Advance Formal Verification team at AMD. As a key member of our team, you will be responsible for providing formal functional and security verification for a broad range of IPs, including input-output virtualization, PCIe Root-Complex/End-Point, inter-chiplet high-speed connections, and more.
Key Responsibilities:- Collaborate with architects and designers to understand design intents and create formal verification plans for design blocks.
- Write and debug properties to verify design, analyze signatures, and push for resolution.
- Optimize runtime using formal techniques and collect and report status and progress.
- Improve formal setups based on feedback from reviews, metrics, and other sources.
- For senior-level positions, lead and coordinate verification activities for a small team, train and coach junior engineers, develop working procedures, flows, and infrastructure, and handle complicated formal problems.
- 5+ years of combined ASIC/FPGA design and verification experience.
- Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods.
- Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off, and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.).
- Extensive experience verifying complex, packet, or control-based designs.
- Familiarity with industry-standard high-speed protocols such as PCIe, CXL, SATA, USB, AXI, UCIe, etc.
- Experience with verification of Hardware-Firmware interaction is highly desirable.
- BS (or higher) degree in Electronics/Electrical or Computer Engineering desired.
Vancouver, Calgary, Toronto, or Ottawa.
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Formal Verification Engineer
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