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Senior ASIC Design Engineer

2 months ago

Markham, Ontario, Canada Qualcomm Full time
Job Summary

We are seeking a highly skilled Senior ASIC Design Engineer to join our Compute DSP/AI Processor Design Team at Qualcomm. As a key member of our team, you will be responsible for developing innovative hardware solutions to support AI/ML and video processing systems in our Snapdragon processors.

Key Responsibilities
  • Design and develop module, hard-macro, and floor planning specifications for digital compute processing cores, bus interfaces, and other system-on-a-chip functions.
  • Analyze and present performance, area, power, and system cost tradeoffs for hard macros using constraint, timing, and floorplan driven optimizations.
  • Contribute to and drive design, floor planning, and implementation meetings within a multi-disciplinary team.
  • Implement and debug timing constraints, RTL, Design for Test (DFT), and clock functions.
  • Perform netlist synthesis, Formal Verification, and Static Timing Analysis of hard macros.
  • Implement ECOs using automated design flows.
  • Complete design checks and analysis such as: lint, CDC, power intent, and static timing reports.
  • Develop methodology and automation for design/synthesis using tcl/make/python scripts.
Requirements
  • 3+ years of experience in ASIC design and netlist implementation.
  • Authorization to work legally in Canada.
Preferred Qualifications
  • Proven experience implementing high-speed logic designs with RAM and several clock domains.
  • Strong verbal and written communication skills to concisely evaluate and deliver specifications, plans, and design analyses.
  • Detail-oriented with strong analytical, critical thinking, and debugging skills.
  • Collaborative and able to adapt to challenging team objectives in a multi-national organization.
  • Understanding of ASIC/VLSI design concepts, bus interfaces, clock crossing, RAM and FIFO integration, ASIC clock network analysis, static timing analysis debug strategy, timing constraints development and debug, and power optimization.
  • Proven design and implementation skills using several of the following languages and tools: synthesis, static timing, power intent and analysis, formal verification, design/DV, and scripting languages.