Senior Mixed Signal Co-Simulation Verification Engineer

3 weeks ago


Mississauga, Ontario, Canada Synopsys Full time
Job Title: Senior Mixed Signal Co-Simulation Verification Engineer

We are seeking a highly motivated and innovative mixed signal co-simulation verification engineer to join our team. As a key member of our mixed-signal design team, you will be responsible for verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB 2/3/4 SERDES products.

Responsibilities:
  • Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
  • Analyze and verify the functionalities of SERDES
  • Define and track verification test plans
  • Debug simulation failures in both analog and digital domains
  • Create top-level analog testbenches for SERDES
  • Perform physical layout reliability analysis for SERDES
Requirements:
  • BSEE or related degree and 1+ years verification experience
  • Strong knowledge of analog circuitry such as bandgap, opamp, PLL, Transmitter/Receiver designs etc.
  • Ability to write scripts in languages such as Perl, Python, and Unix shell
  • Familiar with Verilog and SystemVerilog
About Synopsys

Synopsys is at the heart of the innovations that change the way we work and play. We're powering the Era of Smart Everything with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.



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