Senior FPGA Engineer
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Key Responsibilities
- Design and implement FPGA logic using SystemVerilog, from micro-architecture through to timing-clean implementation.
- Analyse and manage Clock Domain Crossings (CDC), including synchronization strategies and CDC verification.
- Own the FPGA synthesis flow, including tool configuration, timing constraints, and timing closure.
- Analyse synthesis and timing reports to identify and resolve timing, congestion, and resource utilisation issues.
- Collaborate with hardware, verification, and systems teams to ensure designs are robust, testable, and implementation-ready.
- Contribute to design reviews, technical documentation, and improvements to FPGA design processes. Must-Have Experience
- 10-15 years of hands-on FPGA design experience, with the ability to quickly take ownership of complex designs.
- Strong, current experience with SystemVerilog.
- Practical experience with CDC analysis and implementation.
- Hands-on experience configuring FPGA synthesis tools.
- Strong understanding of SDC timing constraints and constraint development.
- Proven ability to analyse synthesis/timing reports and drive designs through timing closure.
- Ability to work full-time, on-site in Ottawa. Nice to Have
- Experience with UVM-based verification.
- Scripting experience with Tcl, Python, or similar.
- Familiarity with high-speed interfaces used in optical, networking, or communications products.
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