ASIC Digital Design, Staff Engineer
1 week ago
DDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR PHY IP products. All current and next-generation technologies are being developed by the DDR PHY IP team, where both digital and analog components complement each other in creating high-performance, high-bandwidth, low-latency, and low-power products.
We are looking for a Staff ASIC Digital Design Engineer to join Synopsys' DDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare DDR PHY IP solution. Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solutions; your passion and expertise will shape the next generation of product innovation, performance, and efficiency.
Job Description
- Contribute to all phases of designs of DDR PHY IP from design specification to productization, including a certain level of customer support into their SoCs.
- Design and micro-architect DDR PHY IP writing Verilog and SystemVerilog code and design specifications.
- Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members.
- Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues.
- Maintain and improve design automation flow and process.
Required Skills
- BS in Electrical Engineering with at least 5 years of experience in complex technical development.
- Experience with synthesizable Verilog and SystemVerilog design concepts, coding, and implementation.
- Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques.
- Exhibit excellent communication skills and be self-motivated.
- Understanding of DDR memory and DDR PHY architecture is a plus.
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