Sr. Principal Product Engineer, Silicon Signoff Verification

Senior Principal Product Engineer At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a Senior Principal Product Engineer (8-12+ years industry experience) to lead advanced signoff methodology development, customer enablement, and product deployment activities for Cadence's timing signoff and ECO solutions. The ideal candidate will possess deep expertise in STA, MMMC signoff, ECO convergence, power optimization, signal integrity, and physical implementation, along with strong customer-facing skills and the ability to influence product direction through close collaboration with R&D and strategic semiconductor customers. Drive development and deployment of advanced signoff methodologies covering timing, power, signal integrity, and ECO closure. Collaborate with customers, AE teams, and R&D to resolve complex design closure challenges. Drive signoff correlation across implementation, STA, SPICE, and signoff environments. Setup and hold closure, Power optimization, Crosstalk mitigation, Glitch fixing, Max transition and electrical rule fixing, Multi-view timing closure. Support customer tapeouts and critical project milestones through root-cause analysis and debug. Partner with R&D to prioritize and validate product enhancements and customer-driven requirements. Create deployment collateral, technical presentations, and best-practice methodologies. Drive adoption of emerging technologies including AI-assisted signoff and ECO automation. Required Technical Skills Strong expertise in Static Timing Analysis (STA) Multi-mode multi-corner (MMMC) timing analysis Statistical timing analysis Signal Integrity and Crosstalk Analysis Glitch analysis and fixing methodologies ECO implementation and closure flows Power optimization techniques RC extraction and parasitic analysis Physical implementation and signoff optimization Physical implementation and signoff environments AI-assisted design closure workflows Customer-facing product engineering Large-scale semiconductor design closure Serve as technical lead for strategic customer engagements. Lead technical reviews and customer escalation management. 8-12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering. ~ Strong experience supporting advanced-node SoC/ASIC designs through implementation, timing closure, ECO convergence, and tapeout. ~ Proven experience working directly with semiconductor customers, R&D organizations, and field engineering teams to resolve complex technical challenges. ~ Experience leading technical investigations, driving root-cause analysis, and influencing product enhancements for customer success. ~ Demonstrated ability to independently own strategic customer engagements and drive cross-functional execution. Experience with power-performance-area (PPA) optimization and signoff closure. ~ Experience with customer-facing technical leadership across strategic semiconductor accounts. ~ Experience in ECO closure methodologies, signal integrity analysis, glitch fixing, and timing correlation. ~ Exposure to AI-assisted implementation and signoff workflows is highly desirable. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.
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Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #