ASIC Digital Design Engineer
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Key Responsibilities
Develop digital designs using Verilog, VHDL, and SystemVerilog Create microarchitecture for next-generation power control systems Integrate complex subsystems into SoC designs Coordinate with multisite leads across United States and India Analyze reports and run ASIC development tools
Requirements:
Five to eight years of digital ASIC front-end design experience Expertise with complex multi-clock and multi-power-domain RTL Experience with UPF and power-domain crossing Familiarity with AHB, AXI, SPMI, I2C, and SPI Expertise in Perl and TCL languages Apply ASIC design expertise, RTL development, and low-power methodology to Qualcomm power control systems. #J-18808-Ljbffr
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