Senior Staff Analog Design Engineer
5 days ago
North Census Division SK, Saskatchewan, Canada
SiTime Corp.
Full-time
Free with email or Google
Save this job and keep your search organized
Create a free account to save jobs, create alerts and return to this listing from your dashboard.
Free with email or Google
By continuing, you agree to our Terms & Privacy Policy.
Lead advanced analog design at SiTime in Ottawa, applying CMOS circuit expertise and system-level thinking to precision timing products.
As a Senior Staff Analog Design Engineer, you will provide technical leadership for clock and timing products. The work spans innovative circuit development, PLL building blocks, analog and mixed-signal simulation, and prototype characterization. You will balance performance, schedule, and cost trade-offs while collaborating with test, validation, product engineering, program management, and remote engineering teams.
Key Responsibilities
Define and develop circuits for high-performance timing products Mentor and guide junior analog designers Collaborate with remote engineering teams Support prototype testing, debugging, and lab characterization Provide technical support through production release
Requirements:
Master’s or PhD degree in Electrical Engineering 10+ years in analog or mixed-signal CMOS design Strong integrated circuit design and device physics knowledge PLL, VCO, phase detector, or charge pump experience Cadence simulation and post-layout verification proficiency Apply analog CMOS design, PLL expertise, and technical leadership to SiTime’s advanced timing products in Ottawa. #J-18808-Ljbffr
Key Responsibilities
Define and develop circuits for high-performance timing products Mentor and guide junior analog designers Collaborate with remote engineering teams Support prototype testing, debugging, and lab characterization Provide technical support through production release
Requirements:
Master’s or PhD degree in Electrical Engineering 10+ years in analog or mixed-signal CMOS design Strong integrated circuit design and device physics knowledge PLL, VCO, phase detector, or charge pump experience Cadence simulation and post-layout verification proficiency Apply analog CMOS design, PLL expertise, and technical leadership to SiTime’s advanced timing products in Ottawa. #J-18808-Ljbffr