Serdes Silicon Validation Engineer
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As a Senior High Speed Validation Engineer, you will evaluate high speed electrical and memory interfaces, including PCIe, IEEE 100G CK, OIF 100G CEI, 224G, and UCIe. You will define test plans, bring up silicon, debug findings, present test results, and deliver validation reports. The position requires project leadership, scripting, and automated test instrumentation.
Key Responsibilities
Define test plans and lead validation projects end to endValidate PCIe, Ethernet, UCIe, and related standardsDevelop standardized scripts for testing and data processingAutomate scopes, BERTs, logic analyzers, VNAs, and suppliesDetermine equipment and accessories required for testingRequirements:
Strong understanding of SerDes architectureExperience validating or debugging high speed interfacesPython or C/C++ scripting abilityLaboratory experience with automated test instrumentsData processing experienceBring SerDes, scripting, instrumentation, and compliance expertise to high speed silicon validation within Qualcomm’s ASIC Engineering group.
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