Soc Interconnect Performance Validation Engineer
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This engineering role supports the central Global SoC digital hardware organization responsible for overall silicon quality. You will collaborate with architects, designers, verification engineers, software engineers, and customers. The focus includes on-chip interconnects, bus architecture, transaction stress programs, FIFO behavior, memory hierarchy, and system performance.
Key Responsibilities
Write programs stressing upstream and downstream interconnect transactionsAssess bandwidth, QoS, latency, throughput, and appropriate coverageEvaluate FIFO performance and functionality across designsValidate memory hierarchy, caches, coherency, and consistencySupport performance monitors, interrupt architecture, and debug architectureRequirements:
Digital design fundamentals and on-chip interconnect understandingExperience with NoCs, AXI, AHB, and FIFO designsEmbedded systems expertise with C, C++, Python, and assemblyLogical problem-solving focused on SoC system feature validationEligible degree and related ASIC experience under stated pathwaysUse interconnect expertise, transaction analysis, memory knowledge, and structured programming to strengthen Qualcomm SoC silicon validation.
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