ASIC Engineer

ASIC Engineer (Senior Digital Verification Engineer - FEC) Join Ciena, a global leader in high‑speed connectivity, and help build the future of networking technology. We value a people‑first culture that prioritizes flexible work, individual growth, well‑being, and belonging. Our work has a meaningful social, community, and societal impact. How You Will Contribute As a Senior Digital Verification Engineer, you will be part of a team responsible for implementing innovative verification strategies to simulate and validate functional blocks and subsystems for Ciena’s Forward Error Correction (FEC) IP. You will report to the ASIC Senior Manager and collaborate closely with Digital Design Engineers, Verification Engineers, and Architects. Read and understand the FEC architecture and functional requirements and communicate with FEC designers, DSP modelers, verifiers, systems engineers, and architects. Develop verification, functional coverage, and formal verification test plans. Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods. Create testbench environments and components, agents, scoreboards, and test scenarios using SystemVerilog UVM and C. Perform coverage‑driven verification, monitor regressions, and debug failures with the support of the function’s designer. Provide status updates on verification progress on a regular basis and communicate risks as needed. We’re looking for an individual passionate about innovation, problem‑solving, and collaboration. If you have expertise in Forward Error Correction functions and programming proficiency in C++ and SystemVerilog, you can make a meaningful impact by shaping future ASIC testing and networking solutions. The above lists are intended to describe the general nature and level of work by the selected candidate and are not an exhaustive list of all responsibilities, duties, and skills required. You will learn more about the role during the interview experience. The Must Haves Minimum Bachelor’s degree in Electrical or Computer Engineering. Significant experience using C/C++, SystemVerilog, UVM, SVA, and simulators from major vendors. Proven ability to determine comprehensive digital verification and coverage strategies. The Assets Experience with formal verification methods. Strong background in Forward Error Correction (FEC) and/or DSP. Familiarity with Python, Make, Bash, object‑oriented programming, C, and C++. Proficiency in bug tracking using Jira and code‑management using Git. Pay Range The annual salary for this position is $109,000 – $174,000. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations. This information reflects the primary location for the role. Non‑Sales employees may be eligible for a discretionary incentive bonus; Sales employees may earn a commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package: medical, dental, and vision plans; participation in 401(k) (USA) & DCPP (Canada) with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company‑paid holidays, paid sick leave, and vacation time. We comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Equal Opportunity Employer At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. We value diversity and do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted regarding a job opportunity, please advise Ciena of any accommodation measures you may require. #J-18808-Ljbffr