Senior Digital Verification Engineer
5 hours ago
You Are:You are an accomplished engineer with a passion for digital and mixed-signal verification. Your career is marked by a relentless drive to excel in complex environments, where your expertise in SystemVerilog and UVM-based testbench development sets you apart. You thrive in collaborative settings, actively contributing to cross-functional teams and fostering an inclusive, supportive culture. Your strong analytical skills, attention to detail, and creative problem-solving abilities enable you to navigate intricate verification challenges and deliver robust solutions. What You’ll Be Doing: Develop comprehensive testplans for complex mixed-signal IP, detailing verification strategies and coverage goals. Design and implement UVM-based testbenches using constraint-random verification methodologies to ensure thorough validation. Enhance and modify testbench components such as scoreboards, agents, and sequences to support evolving product features. Write advanced SystemVerilog tests to validate digital and mixed-signal interaction, addressing edge cases and system-level scenarios. Run RTL and GLS regressions, analyze failures, and drive issue resolution working closely with design and architecture teams. Achieve code and functional coverage goals, ensuring verification completeness and regulatory compliance. Explore opportunities for AI adoption to optimize verification flows and improve efficiency. The Impact You’ll Have: Ensure the delivery of high-performance, reliable mixed-signal IP for next-generation products in networking, storage, and connectivity. Enable rapid time-to-market for Synopsys solutions by streamlining verification processes and resolving technical challenges. Drive quality and compliance, reducing risk of field failures and ensuring customer satisfaction. Contribute to the advancement of verification methodologies, introducing innovative approaches and leveraging emerging technologies. Mentor and support team members, fostering a culture of knowledge sharing and technical excellence. Collaborate with global teams, enhancing Synopsys’ reputation as a leader in semiconductor IP and verification. What You’ll Need: \2+ years of ASIC verification experience, with a strong foundation in digital and mixed-signal domains. Hands-on experience writing complex SystemVerilog testcases for advanced verification scenarios. Proven expertise in developing UVM-based testbenches and leveraging constraint-random methodologies. Proficiency with scripting languages such as Python to automate tasks and enhance verification efficiency. Strong analytical thinking and problem-solving abilities, with a track record of resolving technical issues. Excellent organizational and communication skills, enabling effective collaboration and project management. Demonstrated ability to work collaboratively across multiple design teams and disciplines. Who You Are: Innovative thinker, always seeking new ways to improve processes and methodologies. Collaborative team player who values diversity and inclusion. Detail-oriented, with a commitment to delivering high-quality, error-free results. Adaptable and resilient in dynamic, fast-paced environments. Strong communicator, able to translate complex technical concepts for diverse audiences. Proactive problem solver who takes initiative and ownership of outcomes. Who We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. The Team You’ll Be Part Of: Will join a highly experienced mixed-signal design and verification team based in Mississauga, Ontario. Our team is responsible for delivering cutting-edge solutions for Backplane Ethernet, PCIe, SATA, USB 2/3, DisplayPort, MIPI MPHY, CPHY, and DPHY SerDes. We foster a collaborative, inclusive culture where every member’s expertise is valued and innovation is encouraged. Together, we drive the verification of current and next-generation products, ensuring Synopsys remains at the forefront of technology. Rewards & Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards includes both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr
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Senior Digital Verification Engineer
5 hours ago
Mississauga, Canada Synopsys, Inc. Full timeYou AreYou are an accomplished engineer with a passion for digital and mixed-signal verification. Your career is marked by a relentless drive to excel in complex environments, where your expertise in SystemVerilog and UVM-based testbench development sets you apart. You thrive in collaborative settings, actively contributing to cross-functional teams and...
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ASIC Digital Design Sr Staff Engineer
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Mississauga, Canada Synopsys, Inc. Full timeWe Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the...
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Senior Digital
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Mississauga, Canada Synopsys Inc Full timeA leading semiconductor technology company in Mississauga is seeking an accomplished engineer for mixed-signal verification. The successful candidate will have expertise in SystemVerilog and UVM-based testbench development, contributing to the design of high-performance IP. Responsibilities include developing test plans, enhancing testbenches, and...
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Mississauga, Canada Synopsys, Inc. Full timeA leading semiconductor company is seeking an accomplished engineer for ASIC verification in Mississauga. This role involves developing test plans, designing UVM-based testbenches, and collaborating with global teams to deliver high-performance mixed-signal IP. Candidates should have over 2 years of relevant experience, strong skills in SystemVerilog, and...
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ASIC Verification, Principal Engineer
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