Senior Analog Layout Engineer at Ciena
5 days ago
Ahuntsic North, QC, Canada
Ciena Corporation
Full-time
Free with email or Google
Save this job and keep your search organized
Create a free account to save jobs, create alerts and return to this listing from your dashboard.
Free with email or Google
By continuing, you agree to our Terms & Privacy Policy.
Elevate your career with Ciena as a Senior Analog Layout Engineer, specializing in advanced high-speed analog designs. Embrace a flexible, people-first work culture that prioritizes individual growth and well-being.
As a pivotal team member within Ciena’s vibrant setting, you will contribute to the development and implementation of cutting-edge analog layouts for high-speed DAC and ADC circuits. With a strong focus on deep-submicron CMOS and BiCMOS technologies, you'll enhance our success in pivotal telecommunications solutions. Collaboration with experienced senior designers will help you find optimal design solutions aligned with best practices.
Key Responsibilities: • Develop macro level layouts with detailed floor-planning and optimization • Conduct feasibility studies on analog circuit designs • Write scripts to improve layout automation • Perform DRC, LVS, and other verification checks • Mentor junior team members on layout implementation
Requirements: • Bachelor’s degree in Electrical Engineering with 5+ years’ experience • Proficiency in Cadence Virtuoso and similar layout tools • Strong knowledge of analog and mixed signal layouts • Excellent problem-solving and communication skills • Familiarity with deep sub-micron technologies
Drive innovation in high-speed analog layout engineering at Ciena, leveraging your expertise in advanced circuit design.
As a pivotal team member within Ciena’s vibrant setting, you will contribute to the development and implementation of cutting-edge analog layouts for high-speed DAC and ADC circuits. With a strong focus on deep-submicron CMOS and BiCMOS technologies, you'll enhance our success in pivotal telecommunications solutions. Collaboration with experienced senior designers will help you find optimal design solutions aligned with best practices.
Key Responsibilities: • Develop macro level layouts with detailed floor-planning and optimization • Conduct feasibility studies on analog circuit designs • Write scripts to improve layout automation • Perform DRC, LVS, and other verification checks • Mentor junior team members on layout implementation
Requirements: • Bachelor’s degree in Electrical Engineering with 5+ years’ experience • Proficiency in Cadence Virtuoso and similar layout tools • Strong knowledge of analog and mixed signal layouts • Excellent problem-solving and communication skills • Familiarity with deep sub-micron technologies
Drive innovation in high-speed analog layout engineering at Ciena, leveraging your expertise in advanced circuit design.