Design and Technology

3 weeks ago

Saskatoon, Canada Siemens Mobility Full time
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Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics in order to deliver better products in the increasingly complex world of chip, board and system design.

Tessent Embedded Analytics, part of Siemens EDA, is a pioneering developer of analytics and monitoring technology at the heart of the systems-on-chip (SoCs) that power today’s electronic products. Our embedded analytics technology allows product designers to add sophisticated cybersecurity, functional safety and performance tuning features; and it helps resolve critical issues such as increasing system complexity and ever-decreasing time-to-market. We are proud of our technology and selling globally to many of the most respected and most exciting technology companies in the world.

What we’re looking For

Do you have expertise in silicon IP and digital design using RTL languages? We are looking for a highly capable and dedicated Digital Design or Verification Engineer to join our growing team here at Tessent Embedded Analytics. If you can see yourself learning, growing, and succeeding in this exciting position and would relish the opportunity to help shape the development of Tessent EA’s ground-breaking silicon IP then we would love to meet you

Collaborate with design and architecture teams to understand design specifications and develop verification strategies.Develop and execute detailed verification plans for ASIC designs, ensuring comprehensive coverage of all design features and functionalities.Create and maintain reusable, scalable, and robust testbenches using industry-standard verification languages and methodologies (e.g., li>Identify, analyze, and debug design issues, working closely with design engineers to resolve them in a timely manner.Mentor and provide technical guidance to junior verification engineers, fostering a culture of continuous learning and improvement.

What you’ll bring

  • Solid understanding of UVM and constraint random environments.
  • Verification Planning and Management methods skills.
  • Excellent SystemVerilog and Verilog experience including experience of formulating and writing SystemVerilog coverage statements.
  • Experience of creating testbenches for and testing of silicon IP.
  • Familiarity with other verification techniques such as formal and unit level testing.
  • Familiarity with IC design and implementation.
  • Experience in Formal Verification Techniques and Tools.

    A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. Bring your curiosity and creativity and help us shape tomorrow

    Siemens Software.

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